
ARM Instructions
A4-2
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
4.1 Alphabetical list of ARM instructions
Every ARM instruction is listed on the following pages. Each instruction description shows:
• the instruction encoding
• the instruction syntax
• the version of the ARM architecture where the instruction is valid
• any exceptions that apply
• an example in pseudo-code of how the instruction operates
• notes on usage and special cases.
4.1.1 General notes
These notes explain the types of information and abbreviations used on the instruction pages.
Syntax abbreviations
The following abbreviations are used in the instruction pages:
immed_
n
This is an immediate value, where n is the number of bits. For example, an 8-bit immediate
value is represented by:
immed_8
offset_
n
This is an offset value, where n is the number of bits. For example, an 8-bit offset value is
represented by:
offset_8
The same construction is used for signed offsets. For example, an 8-bit signed offset is
represented by:
signed_offset_8
Encoding diagram and assembler syntax
For the conventions used, see Assembler syntax descriptions on page Preface-xiii.
Architecture versions
This gives details of architecture versions where the instruction is valid. For details, see Architecture
versions and variants on page Preface-v.
Exceptions
This gives details of which exceptions can occur during the execution of the instruction. Prefetch Abort is
not listed in general, both because it can occur for any instruction and because if an abort occurred during
instruction fetch, the instruction bit pattern is not known. (Prefetch Abort is however listed for BKPT, since
it can generate a Prefetch Abort exception without these considerations applying.)

ARM Instructions
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
A4-3
Operation
This gives a pseudo-code description of what the instruction does. For details of conventions used in this
pseudo-code, see Pseudo-code descriptions of instructions on page Preface-xii.
Information on usage
Usage sections are included where appropriate to supply suggestions and other information about how to
use the instruction effectively.

ARM Instructions
A4-4
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
4.1.2 ADC
The ADC (Add with Carry) instruction adds the value of <shifter_operand> and the Carry flag to the
value of <Rn> and stores the result in <Rd>. The condition code flags are optionally updated, based on the
result.
Syntax
ADC{<cond>}{S} <Rd>, <Rn>, <shifter_operand>
where:
<cond> Is the condition under which the instruction is executed. The conditions are defined in The
condition field on page A3-5. If <cond> is omitted, the AL (always) condition is used.
S Causes the S bit (bit[20]) in the instruction to be set to 1 and specifies that the instruction
updates the CPSR. If S is omitted, the S bit is set to 0 and the CPSR is not changed by the
instruction. Two types of CPSR update can occur when S is specified:
•If <Rd> is not R15, the N and Z flags are set according to the result of the addition,
and the C and V flags are set according to whether the addition generated a carry
(unsigned overflow) and a signed overflow, respectively. The rest of the CPSR is
unchanged.
•If <Rd> is R15, the SPSR of the current mode is copied to the CPSR. This form of
the instruction is
UNPREDICTABLE if executed in User mode or System mode, because
these modes do not have an SPSR.
<Rd> Specifies the destination register of the instruction.
<Rn> Specifies the register that contains the first operand for the addition.
<shifter_operand>
Specifies the second operand for the addition. The options for this operand are described in
Addressing Mode 1 - Data-processing operands on page A5-2, including how each option
causes the I bit (bit[25]) and the shifter_operand bits (bits[11:0]) to be set in the instruction.
If the I bit is 0 and both bit[7] and bit[4] of shifter_operand are 1, the instruction is not ADC.
Instead, see Extending the instruction set on page A3-27 to determine which instruction it is.
Architecture version
All
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0
cond 0 0 I 0 1 0 1 S Rn Rd shifter_operand

ARM Instructions
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
A4-5
Exceptions
None
Operation
if ConditionPassed(cond) then
Rd = Rn + shifter_operand + C Flag
if S == 1 and Rd == R15 then
CPSR = SPSR
else if S == 1 then
N Flag = Rd[31]
Z Flag = if Rd == 0 then 1 else 0
C Flag = CarryFrom(Rn + shifter_operand + C Flag)
V Flag = OverflowFrom(Rn + shifter_operand + C Flag)
Usage
ADC is used to synthesize multi-word addition. If register pairs R0, R1 and R2, R3 hold 64-bit values (where
R0 and R2 hold the least significant words) the following instructions leave the 64-bit sum in R4, R5:
ADDS R4,R0,R2
ADC R5,R1,R3
If the second instruction is changed from:
ADC R5,R1,R3
to:
ADCS R5,R1,R3
the resulting values of the flags indicate:
N The 64-bit addition produced a negative result.
C An unsigned overflow occurred.
V A signed overflow occurred.
Z The most significant 32 bits are all zero.
The following instruction produces a single-bit Rotate Left with Extend operation (33-bit rotate through the
Carry flag) on R0:
ADCS R0,R0,R0
See Data-processing operands - Rotate right with extend on page A5-17 for information on how to perform
a similar rotation to the right.